1. Field of Invention
The present invention relates to communication systems. In particular, the present invention relates to a demodulator using block codes within a phase locked loop (PLL) to track the phase of an input modulated signal for high performance at a low signal-to-noise ratio.
2. Discussion of the Related Art
In communication systems, particularly digital communication systems comprising a communication transmitter for digital data transmission and a communication receiver for digital data reception via a channel, it is customary to impress intelligent information to be conveyed onto a carrier for transmission by one of many different modulation techniques, including binary phase shift keying (BPSK) modulation or quaternary phase shift keying (QPSK) modulation. When information is modulated onto a carrier, and a modulated signal is transmitted from the transmitter, the phase space of the receiver generally differs from that of the transmitter due to frequency difference between the local oscillators at the transmitter and receiver and the effect of varying delays and frequency shifts in the propagation path between the two sites.
To track and coherently demodulate the modulated signal received from a transmitter, it is necessary for the receiver to form an estimate of the transmitter's phase so that the tumbling received signals may be transformed back into the fixed phase space of the transmitter. This process is known as “phase tracking.” Conventionally, there are a number of different types of phase tracking loops employing phase locked principles such as squaring loops, Costas tracking loops, and decision-directed feedback loops for performing phase tracking of either a BPSK or QPSK modulated signal. A commonly used method for performing this type of phase tracking is a digital decision directed phase locked loop (DD-PLL). The basic principle of decision directed phase locked loops (DD-PLLs) is well known as described in the classic “Telecommunication Systems Engineering” text by William C. Lindsey and Marvin K. Simon, originally published by Prentice-Hall in 1973, and the “Digital Communications” text by Kamilo Feher, originally published by Prentice-Hall in 1983 and republished by Noble Publishing Corp. in 1997. Generally, the input to a digital decision directed phase locked loop (DD-PLL) typically consists of only the phase angles of a sequence of complex data sample pairs obtained by down converting the incoming BPSK or QPSK modulated signal to a baseband quadrature (orthogonal) pair, IQ digit combination, passing these through matched filters and sampling the results at the symbol rate. This sampled pair may be considered as a complex variable in rectangular form. The complex variable is converted to polar form to produce the equivalent variable pair. The apparent incoming phase is referenced to the currently estimated phase (i.e. the tracked phase) to form the phase difference. The phase difference between the incoming phase and the estimated phase is influenced by the true difference between the phase systems of the transmitter and the receiver, by phase and thermal noise present at the receiver, and also by the symbol's data content which changes the angle by a multiple of π/2 for QPSK or of π for BPSK. The polar form is then transformed back into the rectangular form, for subsequent processing, including soft decision decoding when error control is being utilized.
In conventional phase tracking circuits, the effect of the data content on the phase difference between the incoming phase and the estimated phase is compensated by making a “hard” decision on the data content of each individual BPSK or QPSK symbol on the rectangular coordinates. A standard phase detector generates phase error measurements for each BPSK or QPSK symbol, based on the hard decision of each symbol. In the absence of noise in the baseband quadrature pair, the estimated phase decision, which is based on each individual BPSK or QPSK symbol, is always correct so that the resultant phase error measurement equals the true difference between the phase systems of the transmitter and the receiver. The value of the resultant phase error measurement is then filtered to yield an updated estimate for use at the next symbol epoch, forming a classical servo loop. In practice, noise is always present so that the resultant phase error measurement may be grossly distorted, especially when an incorrect decision is made in converting the phase difference between the incoming phase and the estimated phase to the resultant phase error measurement. As long as the error rate is small, many existing symbol-by-symbol decision directed phase locked loops (DD-PLLs) perform well. However, at low signal-to-noise ratios, the Bit Error Rate (BER) can be relatively high which means that the phase detector can also be unreliable. The effect of incorrect decisions, together with the large amount of noise entering the loop, causes the tracking loop performance to degrade. The deviation of the tracked phase variable increases faster than the signal to noise ratio degrades.
Therefore, conventional decision directed phase locked loops (DD-PLLs) may fail to adequately reduce deviation of phase tracking of either a binary phase shift keying (BPSK) or a quaternary phase shift keying (QPSK) modulated signal, and to minimize error rate for recovered data. This consequence is particularly damaging for digital communication systems such as satellite communication systems that utilize large constellation signal sets to communicate at very low signal-to-noise ratios—as, for example, with error correcting codes. During testing, it was observed that the failure rate of the demodulation process was relatively high when the incoming carrier was offset in frequency from that of the demodulator.